1. Field of the Invention
The present invention relates to an electrically data rewritable non-volatile semiconductor memory device, to an electronic card using the same and to an electronic apparatus. In particular, the present invention relates to read/write control with respect to memory cell arrays formed of the non-volatile semiconductor devices, and is applied to NAND type flash memories, for example.
2. Description of the Related Art
Of electrically data rewritable non-volatile semiconductor memory devices, a batch erasable flash memory stores data by varying an amount of charges injected in a floating gate of a memory cell transistor to change the threshold voltage thereof at the data erase/write operation. For example, when electrons are ejected from the floating gate to make negative the threshold voltage of the memory cell transistor, data “0” is stored, while the electrons are injected to make positive the threshold voltage, thereby storing data “1”. Electron ejection/injection is carried out between a floating gate and a semiconductor substrate via a tunnel oxide film. For this reason, the tunnel oxide film is degraded with an increase of the number of data rewriting times. When the tunnel oxide film is degraded, electrons injected to the floating gate leaks through the tunnel oxide film. As a result, it is difficult to hold the written data in the memory cell transistor. In most of flash memories, the number of rewritable times is one hundred thousand to one million times per memory cell transistor.
Recently, many control systems using the flash memory employ error correction system to take suitable steps for the case where data is broken down to cause data error. During the data error is corrected by using the error correction system, many data rewriting is performed. For example, even if one bit of 528-byte memory cell array has an error, the error correction system corrects the one-byterror through many data rewriting operations. Conventionally, the error correction system has been included in an exclusive controller chip designed to have specialized operations in order to reduce the cost of the flash memory and making error corrections at high speed.
On the other hand, in the control system of an electronic apparatus using the flash memory, a processor unit fetches boot programs for booting the system at the start-up (boot) time. The boot programs include data for controlling the flash memory and error correction programs.
FIG. 20 is a block diagram showing the configuration of a control system using a conventional NAND flash memory.
In the figure, a microprocessor (MPU) 103 is connected to a ROM 104, an SRAM 102 and a NAND flash memory 105 via a system I/O bus line. The MPU 103 reads the system boot programs from the ROM 104 when the system starts up, and controls the SRAM 102 and the NAND flash memory 105. The system boot programs include codes for making error corrections on data of the NAND flash memory 105. The NAND flash memory 105 is used as a file storage in a similar manner as a magnetic disk, and also, is used as an image memory in a digital camera and the like.
The technique of providing the error correction system to the flash memory is disclosed in the following documents.
Japanese Patent No. 3272903 Specification
Jpn. Pat. Aplln. KOAKI Publication No. 2001-14888 T. Tanzawa et al., “A Compact On-chip ECC for Low Cost Flash Memories”, 1996 symposium on VLSI circuits Digest of Technical Papers
As described above, the system using the conventional flash memory requires additional devices such as a controller chip for making error corrections and a ROM for storing boot programs. For this reason, there is a problem that many constituent devices are needed to compose the control system.